1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an integrated circuit which employs a multilevel interconnect structure. The interconnect structure includes interconnect lines which are vertically and horizontally spaced from each other by an intralevel and an interlevel dielectric structure having a low dielectric constant. By offsetting or staggering interconnect lines relative to each other on dissimilar topological levels, a higher density interconnect structure can be produced with minimal electric field coupling between the interconnect lines.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend partially parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are covered by a dielectric material. The layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material; a suitable material includes Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and dielectrically spaced above an underlying conductor or substrate by a dielectric thickness T.sub.d1. Each conductor is dielectrically spaced from other conductors within the same level of conductors (i.e., substantially coplanar conductors) by a distance T.sub.d2. Accordingly, capacitance between vertically spaced conductors, or interlevel capacitance C.sub.LS is determined as follows: EQU C.sub.LS .apprxeq.eW.sub.L L/T.sub.d1 (Eq. 1)
Further, capacitance between horizontally spaced, substantially coplanar conductors, or intralevel capacitance C.sub.LL is determined as follows: EQU C.sub.LL .apprxeq.et.sub.c L/T.sub.d2 (Eq. 2),
where e is the permitivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), W.sub.L is the conductor width, and L is the conductor length. Resistance of the conductor is calculated as follows: EQU R=(rL)/W.sub.L T.sub.c (Eq. 3),
where r represents resistivity of the conductive material, and T.sub.c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate as follows the propagation delay or coupling of a conductor to an adjacent conductor: EQU RC.sub.LS .apprxeq.reL.sup.2 /T.sub.c T.sub.d1 EQU RC.sub.LL .apprxeq.reL.sup.2 /W.sub.L T.sub.d2
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay and/or capacitive coupling be minimized as much as possible given the geometric constraints of the semiconductor topography.
Propagation delay is shown to be a function of both capacitance C.sub.LS as well as capacitance C.sub.LL. Accordingly, propagation delay is determined by parasitic capacitance values between conductors spaced on the same horizontal level (C.sub.LL), and parasitic capacitance values between conductors spaced on different horizontal levels (C.sub.LS). As circuit density increases, lateral spacing as well as vertical spacing between conductors decreases, and C.sub.LL and C.sub.LS deleteriously affect high speed signals forwarded through conductors within a bus. Minimum spacing between conductors on the same level is generally mandated by minimum spacing rules which have steadily decreased over the years. Moreover, planarization techniques and small aspect ratios of level-to-level contacts have forced thin interlevel dielectrics and thereby have decreased the vertical spacing between conductors. A trend, therefore, has been toward reducing both vertical and horizontal spacing between conductors to achieve a dense multilevel interconnect structure associated with VLSI applications.
Increases in parasitic capacitance pose two major problems. First, an increase in parasitic capacitance generally causes an increase in the time at which a transition on the one end of the conductor occurs at the other end. Increase in transition time (i.e., increase in speed degradation) thereby requires a longer drive period. If the conductor extends across a critical speed path, speed degragation on the line will jeopardize functionality of the overall circuit. Second, a larger parasitic capacitance causes an increase in crosstalk noise. A conductor which does not transition, nonetheless receives crosstalk noise from neighboring lines which do. Increase in transition time and crosstalk noise is primarily a function of the geometric space between conductors as well as the dielectric constant (permittivity) of the interposed dielectric. Closely spaced conductors experience a greater fringing field effect than sparsely spaced conductors, regardless of the dielectric constant. Therefore, while it would be beneficial to produce a dielectric having a low dielectric constant, the dielectric must also be sufficiently large in lateral size and thickness in order to optimally minimize fringing fields between conductors.
It is thereby important to minimize propagation delay especially in critical speed paths and/or between conductors which are spaced close to one another. A need arises for reducing propagation delay and cross coupling noise by somehow maximizing the amount of dielectric between conductors and minimizing the dielectric constant of dielectric in critical areas directly between those conductors. The desired configuration must be one which provides maximum lateral and vertical spacing between densely arranged conductors, and also provides optimal dielectric material with low dielectric constant in critical areas.